The present invention generally relates to semiconductor devices, and more particularly to vertical field effect transistors (VFETs).
Field effect transistors (FETs) are typically formed on semiconductor substrates and include a channel region disposed between source and drain regions, and a gate configured to electrically connect the source and drain regions through the channel region. Structures where the channel region is parallel to the main surface of the substrate are referred to as planar FET structures, while structures where the channel region is perpendicular to the main surface of the substrate are referred to as vertical FETs (VFETs). Thus, in a VFET device the direction of the current flow between the source and drain regions is normal (perpendicular) to the main surface of the substrate.
A typical VFET device includes a vertical fin or nanowire that extends upward from the substrate. The fin or nanowire forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin or nanowire sidewalls.